1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
A distance between a contact electrode and a gate electrode is reduced in accordance with scaling, and a significant increase in parasitic capacitance between the gate electrode and the contact electrode causes a significant increase in parasitic capacitance of the gate electrode, and causes degradation of a circuit operation speed and an increase in load capacitance, which lead to an increase in power consumption.
As the means for solving this problem, a gate electrode is formed at the front surface of an active area layer through a gate insulating film, and a source and a drain are formed at the active area layer on both sides of the gate electrode. A device structure and a method of manufacturing the same are suggested in which a contact electrode is provided at the rear surface of the active area layer to be connected to the rear surface of the source/drain (for example, see JP-A-2004-079645).
With scaling and an increase in the size of a system, the number of interconnect layers rapidly increases. For this reason, deterioration in yield or interconnect delay becomes problematic.
As the means for solving this problem, a so-called rear contact electrode and a rear interconnect are used in combination, thereby improving the utility of interconnects and achieving reduction in the number of interconnect layers and improvement in the integration (for example, see JP-A-05-267563).
In the above-described rear contact structure, the contact electrode is connected directly to the diffusion layer. Generally, when the contact electrode is connected from the front surface of the diffusion layer, a low-resistance layer such as a silicide layer is formed at the front surface of the diffusion layer, and the contact electrode is connected to the low-resistance layer, thereby reducing contact resistance. However, it is difficult to form a low-resistance layer such as a silicide layer at the rear surface of the diffusion layer, so the rear contact electrode is inevitably connected directly to the diffusion layer. This causes an increase in contact resistance and degradation in operation speed.
That is, the existing rear contact electrode and rear interconnect allows reduction in parasitic capacitance, but contact resistance between the rear contact electrode and the diffusion layer increases, deterioration in performance of a MOSFET or a variation in performance increases, which leads to deterioration in performance of a semiconductor device.
This is because an impurity concentration of the diffusion layer formed at a silicon layer in contact with a buried oxide layer (BOX) in an SOI substrate silicon layer decreases in a depth direction (rear direction) rather than the front surface due to the introduction of an impurity by ion implantation from the front surface of the silicon layer or the like.
In order to increase an impurity concentration at the interface of the buried oxide layer, it is necessary to increase ion implantation energy or to expand heat treatment after ion implantation. However, when this happens, a short channel effect of MOSFET characteristics increases, and deterioration in performance and a variation in performance increases.
Further, when a front interconnect is used, with the progress of miniaturization, the distance between the gate electrode and the contact electrode becomes closer. For this reason, parasitic capacitance between the gate electrode and the contact electrode or the diffusion layer relatively increases, and performance of a semiconductor device is deteriorated.